Peripheral component interconnect PCI Express (or “PCIe”) is a high performance, generic and scalable system interconnect bus for a wide variety of applications ranging from personal computers to embedded applications. PCIe implements a serial, full duplex, multi-lane, point-to-point interconnect, packet-based, and switch-based technology. Current versions of PCIe buses allow for a transfer rate of 2.5 Gb/Sec per lane, with a total of 32 lanes.
FIG. 1 shows an illustration of a typical architecture 100 of a computing device that includes a PCIe fabric. A host bridge 110 is coupled to endpoints 120, a CPU 130, a memory 140, and a switch 150. The peripheral components are connected through endpoints 120-1 to 120-N (generally referred to as 120). Multiple point-to-point connections are accomplished by the switch 150, which provides the fanout for the I/O bus. The switch 150 provides peer-to-peer communication between different endpoints 120. That is, traffic between the switch 150 and endpoints 120 that does not involve cache-coherent memory transfers, is not forwarded to the host bridge 110. The switch 150 is shown as a separate logical element but it could be integrated into the host bridge 110.
The roundtrip time of a PCIe bus is a major factor in degrading the performance of the bus. The roundtrip time is the time period elapsed from the transmission of data, for example, by the switch 150, to the acknowledgment of the data reception by a PCIe endpoint 120. The roundtrip time of a PCIe bus depends on the delay of a link between the switch 150 and a PCIe endpoint 120. Typically, this delay is due to an Acknowledgment (ACK) and flow control update latencies caused by the layers of a PCIe bus.
In the abstract, the PCIe is a layered protocol bus, consisting of a transaction layer, a data link layer, and a physical layer. The data link layer waits to receive an ACK signal for transaction layer packets during a predefined time window. If an ACK signal is not received during this time window, unacknowledged packets are re-transmitted. This results in inefficient bandwidth utilization of the bus as it requires retransmission of packets with no data integrity problem. That is, a high latency between the PCIe components may cause poor bandwidth utilization.
In the current technology, peripheral devices are physically coupled to the PCIe components (e.g., endpoints, switches, etc.). In fact, these PCIe components are always connected on the same electric board. Thus, the roundtrip time is typically very short and the PCIe is not designed to properly operate in a high latency environment.
In the related art, a few solutions have been proposed to wirelessly connect peripheral devices. These solutions are addressed to replace bus connectivity where the latency of the bus is not critical to the operation of the devices. However, connectivity of PCIe components over the air would significantly increase the latency of the link, and therefore degrade the performance of the bus.
It would be therefore advantageous to provide a solution that enables the wireless connection between all types of peripheral devices to the computing device.